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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Delay Switching Characteristics
Table 27: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
IDELAYCTRL
T DLYCCO_RDY
Reset to Ready for IDELAYCTRL
3.22
3.22
3.22
3.22
3.22
μs
F IDELAYCTRL_REF
IDELAYCTRL_REF_
Attribute REFCLK frequency =
Attribute REFCLK frequency =
REFCLK precision
200.00 (1)
300.00 (1)
200.00
300.00
±10
200.00
300.00
±10
200.00
N/A
±10
200.00
N/A
±10
200.00
N/A
±10
MHz
MHz
MHz
PRECISION
T IDELAYCTRL_RPW
Minimum Reset pulse width
52.00
52.00
52.00
52.00
52.00
ns
IDELAY/ODELAY
T IDELAYRESOLUTION
IDELAY/ODELAY chain delay resolution
1/(32 x 2 x F REF )
ps
Pattern dependent period jitter in delay
0
0
0
0
0
ps
chain for clock pattern. (2)
per tap
Pattern dependent period jitter in delay
±5
±5
±5
±5
±5
ps
T IDELAYPAT_JIT and
T ODELAYPAT_JIT
chain for random data pattern
(PRBS 23) (3)
per tap
Pattern dependent period jitter in delay
±9
±9
±9
±9
±9
ps
chain for random data pattern
(PRBS 23) (4)
per tap
T IDELAY_CLK_MAX /
T ODELAY_CLK_MAX
T IDCCK_CE /
T IDCKC_CE
T ODCCK_CE /
T ODCKC_CE
T IDCCK_INC /
T IDCKC_INC
T ODCCK_INC /
T ODCKC_INC
T IDCCK_RST /
T IDCKC_RST
T ODCCK_RST /
T ODCKC_RST
T IDDO_IDATAIN
T ODDO_ODATAIN
Maximum frequency of CLK input to
IDELAY/ODELAY
CE pin Setup/Hold with respect to C for
IDELAY
CE pin Setup/Hold with respect to C for
ODELAY
INC pin Setup/Hold with respect to C for
IDELAY
INC pin Setup/Hold with respect to C for
ODELAY
RST pin Setup/Hold with respect to C for
IDELAY
RST pin Setup/Hold with respect to C for
ODELAY
Propagation delay through IDELAY
Propagation delay through ODELAY
800.00
0.11/0.10
0.14/0.03
0.10/0.14
0.10/0.07
0.13/0.08
0.16/0.04
Note 5
Note 5
800.00
0.14/0.12
0.16/0.04
0.12/0.16
0.12/0.08
0.14/0.10
0.19/0.06
Note 5
Note 5
710.00
0.18/0.14
0.19/0.05
0.14/0.20
0.13/0.09
0.16/0.12
0.24/0.08
Note 5
Note 5
710.00
0.18/0.14
0.19/0.05
0.14/0.20
0.13/0.09
0.16/0.12
0.24/0.08
Note 5
Note 5
710.00
0.14/0.16
0.28/0.06
0.10/0.23
0.19/0.16
0.22/0.19
0.32/0.11
Note 5
Note 5
MHz
ns
ns
ns
ns
ns
ns
ps
ps
Notes:
1.
2.
3.
4.
5.
Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
When HIGH_PERFORMANCE mode is set to TRUE.
When HIGH_PERFORMANCE mode is set to FALSE.
Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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